Series resistance and gate leakage correction for improved border trap analysis of Al2O3/InGaAs gate stacks

As the size of electronic devices scales down, series resistance (R-S) and gate leakage effects are commonly observed in electrical measurement of metal-oxide-semiconductor gate stacks. As a result of their effects on device characteristics, these phenomena complicate the analysis of border trap density (N-bt) in the gate insulator using capacitance-voltage (C-V) and conductance-voltage (G-V) measurements. In this work, we develop methods to correct for the effects of R-S and gate leakage in Al2O3/InGaAs gate stacks to enable reliable fitting of C-V and G-V data to determine Nbt. When tested using data from Pd/Al2O3/InGaAs gate stacks, the RS correction method successfully removes the R-S-induced high frequency dispersion in the accumulation region of the C-V curves and provides an accurate extraction of R-S and N-bt. The gate leakage correction method is tested on gate stacks with high gate leakage current of similar to 25 mu A at 2V bias, and is found to effectively fit capacitance and conductance data, to achieve consistent N-bt extraction. The compatibility of these two methods is confirmed by analysis of data obtained from gate stacks with both substantial R-S and gate leakage. Published by AIP Publishing.