Layer-by-layer assembled charge-trap memory devices with adjustable electronic properties

被引:239
作者
Lee, Jang-Sik
Cho, Jinhan
Lee, Chiyoung
Kim, Inpyo
Park, Jeongju
Kim, Yong-Mu
Shin, Hyunjung
Lee, Jaegab
Caruso, Frank
机构
[1] Kookmin Univ, Sch Adv Mat Engn, Seoul 136702, South Korea
[2] Univ Melbourne, Ctr Nanosci & Nanotechnol, Dept Chem & Biomol Engn, Melbourne, Vic 3010, Australia
基金
欧洲研究理事会; 澳大利亚研究理事会;
关键词
D O I
10.1038/nnano.2007.380
中图分类号
TB3 [工程材料学];
学科分类号
0805 ; 080502 ;
摘要
We describe a versatile approach for preparing flash memory devices composed of polyelectrolyte/gold nanoparticle multilayer films. Anionic gold nanoparticles were used as the charge storage elements, and poly(allylamine)/poly(styrenesulfonate) multilayers deposited onto hafnium oxide (HfO2)-coated silicon substrates formed the insulating layers. The top contact was formed by depositing HfO2 and platinum. In this study, we investigated the effect of increasing the number of polyelectrolyte and gold nanoparticle layers on memory performance, including the size of the memory window (the critical voltage difference between the 'programmed' and 'erased' states of the devices) and programming speed. We observed a maximum memory window of about 1.8 V, with a stored electron density of 4.2 x 10(12) cm(-2) in the gold nanoparticle layers, when the devices consist of three polyelectrolyte/gold nanoparticle layers. The reported approach offers new opportunities to prepare nanostructured polyelectrolyte/gold nanoparticle-based memory devices with tailored performance.
引用
收藏
页码:790 / 795
页数:6
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