Using the Hardware/Software co-design methodology to implement an embedded face recognition/verification system on an FPGA

被引：0
|
作者：
Zaki, G. F. [1 ]
Girgis, R. A. [1 ]
Moussa, W. W. [1 ]
Gabran, W. R. [1 ]
机构：
[1] Cairo Univ, Elec & Comm Dept, Giza, Egypt
来源：
2007 INTERNATIONAL CONFERENCE ON MICROELECTRONICS | 2007年
关键词：
digital signal processing; embedded system; face recognition; HW/SW co-design;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
An embedded face recognition/verification system has been implemented on an FPGA. The system recognizes/verifies the user by capturing his/her facial image via a digital image sensor and runs a series of DSP algorithms to reach the decision. It is embedded and small in size allowing it to suit a wide range of applications. It is based on an. FPGA which offers high configurability in the design phase. The Hardware/Software codesign methodology was used which enabled optimizing the system to meet different design constraints including size, cost and power dissipation. A number of DSP algorithms were used or created to detect the face from a background, enhance the image and recognize the person. The Principal Component Analysis algorithm was used for feature extraction.
引用
收藏
页码：13 / 16
页数：4
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