Performance space modeling for hierarchical synthesis of analog integrated circuits

被引：0

作者：

Gielen, G ^{[1
]}

McConaghy, T ^{[1
]}

Eeckelaert, T ^{[1
]}

机构：

[1] Katholieke Univ Leuven, ESAT MICAS, B-3001 Louvain, Belgium

来源：

42ND DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2005 | 2005年

关键词：

hierarchical synthesis;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Automated analog sizing is becoming an unavoidable solution for increasing analog design productivity. The complexity of typical analog SoC subsystems however calls for efficient methods that can handle design hierarchy, in terms of both performance estimation and hierarchical design optimization method. This paper discusses and compares recent developments in this area, with special emphasis on automated modeling and on multi-objective bottom-up hierarchical design.

引用

页码：881 / 886

页数：6

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