Parallel and Pipelining design of SLAM Feature Detection Algorithm in Hardware

被引:0
作者
Liu, Yunjie [1 ]
Wu, Xiaofeng [1 ]
机构
[1] Univ Sydney, Sch Aerosp Mech & Mechatron, Sydney, NSW, Australia
来源
PROCEEDINGS OF THE 2021 IEEE 16TH CONFERENCE ON INDUSTRIAL ELECTRONICS AND APPLICATIONS (ICIEA 2021) | 2021年
关键词
pipelining; SLAM; SURF; FPGA; floating-point arithmetic; SIMULTANEOUS LOCALIZATION; IMAGE;
D O I
10.1109/ICIEA51954.2021.9516430
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
Simultaneous Localization and Mapping (SLAM) is a system used to achieve autonomous positioning and navigation. Feature detection is an important part of a SLAM system as fast and robust image matching is required for the task. A typical feature detection algorithm called Speeded-Up Robust Features (SURF) is used in a robot SLAM system with Moving Object Detection (MOD). This paper describes a modified feature detection algorithm based on Field Programmable Gate Array (FPGA) hardware. The paper focuses on implementing the software algorithm on a hardware platform. The advantage of the parallel and pipelining design of FPGA is fully applied to highly improve the performance and efficiency of the system. By using the FPGA hardware platform, the algorithm can also be implemented easily in an FPGA-based SLAM system afterward to finally use for System-On-Chip (SoC) applications.
引用
收藏
页码:1388 / 1393
页数:6
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