InGaAs FinFETs Directly Integrated on Silicon by Selective Growth in Oxide Cavities

被引:31
作者
Convertino, Clarissa [1 ]
Zota, Cezar [1 ]
Schmid, Heinz [1 ]
Caimi, Daniele [1 ]
Sousa, Marilyne [1 ]
Moselund, Kirsten [1 ]
Czornomaz, Lukas [1 ]
机构
[1] IBM Res GmbH Zurich, Saumerstr 4, CH-8803 Ruschlikon, Switzerland
关键词
III-V; TASE; MOSFETs; Integration;
D O I
10.3390/ma12010087
中图分类号
O64 [物理化学(理论化学)、化学物理学];
学科分类号
070304 ; 081704 ;
摘要
III-V semiconductors are being considered as promising candidates to replace silicon channel for low-power logic and RF applications in advanced technology nodes. InGaAs is particularly suitable as the channel material in n-type metal-oxide-semiconductor field-effect transistors (MOSFETs), due to its high electron mobility. In the present work, we report on InGaAs FinFETs monolithically integrated on silicon substrates. The InGaAs channels are created by metal-organic chemical vapor deposition (MOCVD) epitaxial growth within oxide cavities, a technique referred to as template-assisted selective epitaxy (TASE), which allows for the local integration of different III-V semiconductors on silicon. FinFETs with a gate length down to 20nm are fabricated based on a CMOS-compatible replacement-metal-gate process flow. This includes self-aligned source-drain n(+) InGaAs regrown contacts as well as 4 nm source-drain spacers for gate-contacts isolation. The InGaAs material was examined by scanning transmission electron microscopy (STEM) and the epitaxial structures showed good crystal quality. Furthermore, we demonstrate a controlled InGaAs digital etching process to create doped extensions underneath the source-drain spacer regions. We report a device with gate length of 90 nm and fin width of 40 nm showing on-current of 100 mu A/mu m and subthreshold slope of about 85 mV/dec.
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页数:6
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