A Compact Model for Threshold Voltage of Surrounding-Gate MOSFETs With Localized Interface Trapped Charges

被引：90
作者：
Chiang, Te-Kuang [1 ]
机构：
[1] Natl Univ Kaohsiung, Adv Devices Simulat Lab, Dept Elect Engn, Kaohsiung 811, Taiwan
来源：
IEEE TRANSACTIONS ON ELECTRON DEVICES | 2011年 / 58卷 / 02期
关键词：
Hot-carrier-induced threshold voltage; surrounding-gate MOSFETs; SCALING THEORY;
D O I：
10.1109/TED.2010.2092777
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Based on the perimeter-weighted-sum method and scaling theory, a compact threshold voltage model for surrounding-gate MOSFETs with localized interface trapped charges is developed by considering the effects of equivalent oxide charges on the flat-band voltage. The model shows how various charge conditions such as the positive/negative trapped charges and device structure parameters such as the silicon thickness, oxide thickness, and channel length affect the threshold voltage behavior. The model is verified by the 3-D device simulator and can be efficiently used to explore hot-carrier-induced threshold voltage degradation of the charge-trapped memory device.
引用
收藏
页码：567 / 571
页数：5
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