A Type-3 PLL for Single-Phase Applications

被引:0
|
作者
Bamigbade, Abdullahi [1 ]
Khadkikar, Vinod [1 ]
Al Hosani, Mohamed [2 ]
机构
[1] Khalifa Univ, Adv Power & Energy Ctr, EECS Dept, Masdar City Campus, Abu Dhabi, U Arab Emirates
[2] Abu Dhabi Distribut Co, DSM Dept, Abu Dhabi, U Arab Emirates
关键词
Phase locked-loop (PLL); steady-state error; loop filter; phase margin; gain cross-over frequency; disturbance rejection capability; FREQUENCY-LOCKED LOOP; SYNCHRONIZATION; TIME;
D O I
暂无
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
Different structures of single-phase PLL have been widely developed for the synchronization of single-phase grid-connected power electronic-based equipments. These PLLs mostly employ proportional-integral (PI) controller as loop filter, thereby resulting in a type-2 control system. Hence, they are able to achieve zero steady-state phase error following step changes in frequency and phase of a single-phase input signal. However, when the input signal varies continuously over time in a linear manner, these PLLs exhibit a finite steady-state phase error. Thus, they may not be suitable for applications that require accurate estimation of phase angle when a ramp change in frequency occurs. To overcome this problem without compromising the benefits of type-2 PLLs, a type-3 PLL for single-phase applications is developed in this paper. Through experimental validation and comparison with an advanced single-phase type-2 PLL, the effectiveness of developed type-3 PLL is demonstrated.
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页数:6
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