Tunable SEU-Tolerant Latch

被引:7
作者
She, Xiaoxuan [1 ]
Li, N. [2 ]
Farwell, W. Darresware [3 ]
机构
[1] Fudan Univ, State Key Lab ASIC & Syst, Shanghai 200433, Peoples R China
[2] Gpix Inc, Orlando, FL 33816 USA
[3] RAY Co, Charlotte, NC USA
关键词
Hardened by design; latch; radiation effects; single event upset (SEU); SOFT ERRORS; DELAY; RELIABILITY;
D O I
10.1109/TNS.2010.2087358
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents a single event upset (SEU) hardened latch that can mitigate SEU pulses having a width less than T, where T is the longest anticipated duration of SEUs. The propose latch includes a controllable inertial delay inverter. In order to mitigate SEUs with pulse widths less than T, a global controller uses delay locked loops to control the rise and fall times of the controllable inertial delay inverter in each latch to be equal to T. This allows T to be adjustable for different applications and environmental conditions. This technique introduces little area penalty and does not adversely affect propagation delay.
引用
收藏
页码:3787 / 3794
页数:8
相关论文
共 29 条
[11]  
ingh J, 2007, P INT C INF TECHN IC, P13
[12]   A NOVEL SEU, MBU AND SHE HANDLING STRATEGY FOR XILINX VIRTEX-4 FPGAS [J].
Iturbe, X. ;
Azkarate, M. ;
Martinez, I. ;
Perez, J. ;
Astarloa, A. .
FPL: 2009 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS, 2009, :569-+
[13]   Characterization of soft errors caused by single event upsets in CMOS processes [J].
Karnik, T ;
Hazucha, P ;
Patel, J .
IEEE TRANSACTIONS ON DEPENDABLE AND SECURE COMPUTING, 2004, 1 (02) :128-143
[14]   A single-event-hardened phase-locked loop fabricated in 130 nm CMOS [J].
Loveless, T. D. ;
Massengill, L. W. ;
Bhuva, B. L. ;
Holman, W. T. ;
Reed, R. A. ;
McMorrow, D. ;
Melinger, J. S. ;
Jenkins, P. .
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2007, 54 (06) :2012-2020
[15]   A digitally programmable delay element: Design and analysis [J].
Maymandi-Nejad, M ;
Sachdev, M .
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2003, 11 (05) :871-878
[16]  
Nagpal C, 2008, DES AUT TEST EUROPE, P312
[17]   Construction of SEU Tolerant Flip-Flops Allowing Enhanced Scan Delay Fault Testing [J].
Namba, Kazuteru ;
Ikeda, Takashi ;
Ito, Hideo .
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2010, 18 (09) :1265-1276
[18]  
Naseer R, 2006, IEEE INT SYMP CIRC S, P3890
[19]   Low-cost highly-robust hardened cells using blocking feedback transistors [J].
Nicolaidis, Michael ;
Perez, Renaud ;
Alexandrescu, Dan .
26TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 2008, :371-+
[20]  
Oliveira R, 2007, ISQED 2007: PROCEEDINGS OF THE EIGHTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, P905