A Low-Power IP Design of Viterbi Decoder with Dynamic Threshold Setting

被引：0

作者：

Lin, Yi-Ming ^{[1
]}

Liu, Wan-Ching ^{[1
]}

Chang, Li-Yuan ^{[1
]}

Lien, Chih-Yuan ^{[2
]}

Chen, Pei-Yin ^{[1
]}

Chen, Shung-Chih ^{[3
]}

机构：

[1] Natl Cheng Kung Univ, Dept Comp Sci & Informat Engn, Tainan 701, Taiwan

[2] Chia Nan Univ Pharm & Sci, Dept Informat Management, Tainan 717, Taiwan

[3] Southern Taiwan Univ, Dept Elect Engn, Tainan 710, Taiwan

来源：

2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS | 2010年

关键词：

CONVOLUTIONAL-CODES; ALGORITHM;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, a low-power design of Viterbi decoder is presented. Based on the adaptive Viterbi algorithm, we use a dynamic setting method to set various threshold values for different decoding stages under a particular SNR and efficient reduce the average number of survivor paths. Furthermore, a flexible soft intellectual property core and an auxiliary software system for low-power Viterbi decoder are proposed. In the VLSI realization, we apply the clock-gating technique to disable the activation of registers for nonsurvivor paths. Hence, the power consumption can be reduced. Compared with others, our design requires the lower power consumption for the same SNR condition.

引用

页码：585 / 588

页数：4

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