Optimal Design of 6T SRAM Bitcells for Ultra Low-Voltage Operation

被引：0

作者：

Ghonem, Amgad A. ^{[1
]}

Farid, Mostafa F. ^{[1
]}

Dessouky, Mohamed ^{[1
]}

机构：

[1] Ain Shams Univ, Integrated Circuits Lab, Cairo, Egypt

来源：

2015 IEEE CONFERENCE ON ELECTRONICS, CIRCUITS, AND SYSTEMS (ICECS) | 2015年

关键词：

SRAM; LOW VOLTAGE; ASSIST TECHNIQUES;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Embedded SRAM is involved in many low-energy applications, e.g. stand-alone wireless sensor nodes. SRAMs have the highest energy contribution in such applications. Energy consumption can be decreased by lowering the supply voltage. However, SRAM bitcells impose a lower bound on the supply voltage. In this paper, ultra low-voltage SRAM design optimization is investigated in a 65nm technology. It is shown that the bitcell design at low-voltages is fairly different than that at nominal ones. Using aggressive write/read-assist techniques, the well-known 6-transistor bitcell can operate down to 0.5V. Five different optimized design options are compared. Write-optimized bitcells are shown to be optimal for ultra low-voltage operation.

引用

页码：454 / 457

页数：4