A Precision, Energy-Efficient, Oversampling, Noise-Shaping Differential SAR Capacitance-to-Digital Converter

被引:26
|
作者
Alhoshany, Abdulaziz [1 ]
Salama, Khaled N. [2 ]
机构
[1] Qassim Univ, Dept Elect Engn, Al Malida 52571, Saudi Arabia
[2] King Abdullah Univ Sci & Technol, Comp Elect & Math Sci & Engn Div, Thuwal 239556900, Saudi Arabia
关键词
Capacitance-to-digital converter (CDC); capacitive sensor interface circuit; CMOS; energy efficient; high-precision capacitive resolution; successive approximation (SAR); THIN-FILMS; DUAL-SLOPE; LOW-POWER; SENSORS; CMOS; ADC; INTERFACE; WIRELESS; OUTPUT;
D O I
10.1109/TIM.2018.2844899
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper introduces an oversampling, noise-shaping differential successive-approximation-register capacitance-to-digital converter (CDC) architecture for interfacing capacitive sensors. The proposed energy-efficient CDC achieves high-precision capacitive resolution by employing oversampling and noise shaping. The switched-capacitor (SC) integrator is inserted between the comparator and the chargeredistribution digital-to-analog converter to implement noise shaping and to make the interface circuit insensitive to parasitic capacitances. An inverter-based operational transconductance amplifier with a common-mode feedback circuit is employed to implement the SC integrator with subthreshold biasing for low voltage and low power. The ring-oscillator-based comparator is implemented to achieve high energy efficiency. The test chip is fabricated in a 0.18-mu m CMOS technology. The proposed CDC experimentally achieves 150 aF absolute resolution and 12.74ENOB with an oversampling ratio of 15 and a sampling clock of 18.51 kHz. The fabricated prototype dissipates 1.2 and 0.39 mu W from analog and digital supplies, respectively, with an energy efficiency figure-of-merit of 187 fJ/conversion step.
引用
收藏
页码:392 / 401
页数:10
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