Low-power CMOS continuous-time filters

A design technique for low-power continuous-time filters using digital CMOS technology is presented, The basic building block is a fully-balanced integrator with its unity-gain frequency determined by a small-signal transconductance and a MOSFET gate capacitance, Integrator excess phase shift is reduced using balanced signal paths, and open-loop gain is increased using low-voltage cascode amplifiers, Two-pole bandpass and five-pole lowpass ladder filters have been implemented in a 1.2 mu m n-well CMOS process, The lowpass prototypes provided 300 kHz-1000 kHz bias-current-tunable -3 dB bandwidth, 67 dB dynamic range with 1% total harmonic distortion (THD), and 30 mu W/pole (300 kHz bandwidth) power dissipation with a 1.5 V supply; the bandpass prototypes had a tunable center frequency of 300 kHz-1000 kHz, Q of 8.5, and power dissipation of 75 mu W/pole (525 kHz center frequency) from a 1.5 V supply, The active filter area was 0.1 mm(2)/pole for both designs.