Performance-driven routing tree construction with buffer insertion, wire sizing under RLC delay model

In this paper, given a multi-terminal net, we propose a new approach to construct a performance-driven rectilinear Steiner tree with simultaneous buffer insertion and wiresizing optimization (PDRST/BW) under a higher order resistance-inductance-capacitance (RLC) delay model. This approach is based on the concept of sharing-buffer insertion and dynamic programming approach combined with a bottom-up rectilinear Steiner tree construction. The performances considered in this paper include the timing delay and the quality of signal waveform. Recently several algorithms have been published addressing the buffer insertion problem, but all these algorithms are not scalable and they can only handle the two-terminal nets or small size multi-terminal nets. Moreover, almost all these algorithms use the Elmore delay model. The experimental results show that our proposed approach is scalable and obtains better performance than those previous approaches for the test signal nets.