Accuracy sensitive word-length selection for algorithm optimization

被引:32
作者
Wadekar, SA [1 ]
Parker, AC [1 ]
机构
[1] Univ So Calif, Dept EE Syst, Los Angeles, CA 90089 USA
来源
INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS AND PROCESSORS, PROCEEDINGS | 1998年
关键词
D O I
10.1109/ICCD.1998.727023
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
In typical hardware implementations of an arithmetic-intensive algorithm, designers must determine the word lengths of resources such as adders, multipliers, and registers. This paper presents algorithmic level theory and optimization techniques to select distinct word lengths for each computation which meet the desired accuracy and minimize the design cost for the given performance constraints. The reduction in cost is possible by avoiding unnecessary bit-level computations that do not contribute significantly to the accuracy of the final results. Thus we have introduced a new optimization variable, computation accuracy, into data-path synthesis. Our results show on an average, a 30% reduction in functional-resource area using distinct word lengths as opposed to use of a single optimized word length for the entire algorithm.
引用
收藏
页码:54 / 61
页数:8
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