High Linearity PVT Tolerant 100MS/s Rail-to-Rail ADC Driver With Built-in Sampler in 65nm CMOS

A novel completely inverter-based ADC driver is proposed that relaxes the gain and unity gain bandwidth requirements of the negative feedback loop by making it not see the closed loop gain. This ADC driver has a built-in first order anti alias filter and uses a passive amplifier to provide a rail-to-rail sampled output signal. This design exploits the linearity of current mirrors and achieves 65dB of linearity at the Nyquist rate for a rail-to-rail output. A semi-constant current biasing circuit for inverters has been proposed to minimizing PVT variations in lower technologies. As a proof of concept an ADC driver is designed and implemented in TSMC's 65nm GP CMOS technology. The measured design operates at 100MS/s and has an OIP3 of 40dBm at the Nyquist rate, provides a gain of 8, and samples the signal onto a 1pF output capacitance while drawing 2mA from a 1V supply.