Low-Latency Image Acquisition and Processing with a Programmable Vision-System-on-Chip

被引：0
|
作者：
Doege, Jens [1 ]
Hoppe, Christoph [1 ]
Reichel, Andreas [1 ]
Reichel, Peter [1 ]
Peter, Nico [1 ]
Priwitzer, Holger [1 ]
机构：
[1] Fraunhofer Inst Integrated Circuits IIS, Erlangen, Germany
来源：
2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | 2018年
关键词：
image sensor; Vision-System-on-Chip; VSoC; ASIP; low latency; actuator control; trajectory prediction;
D O I：
10.1109/ISCAS.2018.8351843
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This work aims to demonstrate the benefits of using a Vision-System-on-Chip for image processing tasks with very high latency demands between image acquisition and processing. By leveraging a column-parallel, mixed-signal data path, which is entirely software-defined by three application-specific instruction-set processors (ASIPs), image data within multiple regions of interest can be analyzed at a frame rate of 5 kHz. Thus, with a delay of 0.44 ms, the trajectory of a moving object is analyzed and the object is precisely deflected using a solenoid.
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页数：5
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