Methodology and optimizing of multiple frame format buffering within FPGA H.264/AVC decoder with FRExt

This work evaluated the role of designing the frame buffer of a hardware video decoder, with integrated support for the H.264/AVC codec and its Fidelity Range Extensions (FRFxt) amendment. With focus on organizing external memory data access, the frame buffer was designed to provide intermediate data storage for the decoder, while using an efficient store and load scheme that takes into consideration each frame pixel format of the video data. VHDL was used to model the frame buffer. Exploitation of reconfigurability and post-synthesis FPGA simulations were used to evaluate behavior and scalability while providing an analysis of approaches to adding FRExt to the memory management.