It is widely understood that a close attention to systematic defect issue is required to succeed in a device development and production of 45 nm and beyond. For 45 nm, use of OPC created tremendous challenges in both optimization and validation of proper amount of optical correction needed(1). OPC treatment and variation across wafer have to be controlled and monitored with utmost care where there can be issues near the edge of wafer or under process variations. Generally for 32 nm and beyond, Semiconductor industry's adoption of Immersion and Double Patterning Lithography (DPL) are bringing new challenges in controlling process for best yield. DPL sites can introduce patterning and overlay issues. To introduce a new process or device, Lithography process window must be well understood for faster process development and to prevent catastrophic yield loss. CD and overlay variations must be measured at the most appropriate sites across die and wafer to fully characterize a process. Today Lithography engineers are utilizing various approaches in understanding the process window including CD metrology and Defect inspection using wafers where Focus and Exposure conditions are modulated. Layout and ranges of conditions may vary based on devices and technology. Generally CD metrology provides good sensitivity to the process variation but it is often limited by ability to sample across wafer. Defect inspection provides much wider coverage but requires engineering resources for separating real pattern failure from particles or other pattern noise. In the past Litho process window qualification has been performed requiring much of manual intervention by users. In this paper, we introduce a new technique that enables automatic process window qualification that reduces user intervention while making the procedure repeatable among different users.
