Modeling and design of CMOS UHF voltage multiplier for RFID in an EEPROM compatible process.

被引：28

作者：

Bergeret, Emmanuel ^{[1
]}

Gaubert, Jean ^{[1
]}

Pannier, Philippe ^{[1
]}

Gaultier, Jean Marie ^{[1
]}

机构：

[1] Polytech Univ, Sch Marseilles, Dept Microelect & Telecommun, Lab Mat & Miccoelect Provence,IMT T, F-13451 Marseille, France

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2007年 / 54卷 / 10期

关键词：

MOSFET voltage multiplier; nonlinear model; passive transponders; radio frequency identification (RFID);

D O I：

10.1109/TCSII.2007.902222

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Modeling and design of CMOS ultra-high-frequcncy (UHF) voltage multipliers are presented. These circuits recover power from incident radio frequency (RF) signal and supply battery less UHF RF identification (RFID) transponders. An analytical model of CMOS UHF voltage multipliers is developed. It permits to determine the main design parameters in order to improve multiplier performance. The design of this kind of circuits is then greatly simplified and simulation time is reduced. Thanks to this model, a voltage multiplier is, designed and implemented in a low-cost electrically erasable programmable read-only memory compatible CMOS process without Schottky diodes layers. Measurements results show communication ranges up to 5 m in the U.S. standard.

引用

页码：833 / 837

页数：5

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