Circuit and DFT Techniques for Robust and Low Cost Qualification of a Mixed-signal SoC with Integrated Power Management System

被引：0

作者：

Balasubramanian, Lakshmanan ^{[1
]}

Sabbarwal, Puneet ^{[1
]}

Mittal, Rajesh Kumar ^{[1
]}

Narayanan, Prakash ^{[1
]}

Dash, Ranjit Kumar ^{[1
]}

Kudari, Anand Devendra ^{[1
]}

Manian, Srikanth ^{[1
]}

Polarouthu, Sudhir ^{[1
]}

Parthasarathy, Harikrishna ^{[1
]}

Vijayaraghavan, Ravi C. ^{[1
]}

Turkewadikar, Sachin ^{[1
]}

机构：

[1] Texas Instruments India Private Ltd, Bangalore, Karnataka, India

来源：

2011 DESIGN, AUTOMATION & TEST IN EUROPE (DATE) | 2011年

关键词：

Burn-in; electrical reliability qualification; I-DDQ; analog DFT; power management;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper discusses some specific circuit, and analog DFT techniques and methodologies used in integrated power management (PM) systems to overcome challenges of mixed-signal SoC qualification. They are mainly targeted at achieving the following: 1. Enabling the robust digital and system level test and burn-in (BI) with external supplies by disabling the on-chip PM with robust power-on performance, 2. Minimising external on-board active components in BI board and making the whole BI process more robust, 3. Making the I-DDQ tests more robust, increasing the I-DDQ sensitivity by less error prone design methods and enabling I-DDQ tests possible on analog supplies, and 4. Defining separate BI strategy for the whole PM modules on-chip and enabling it by targeted analog test modes.

引用

页码：551 / 554

页数：4