A Markov Chain Based Hierarchical Algorithm for Fabric-Aware Capacitance Extraction

被引:8
作者
El-Moselhy, Tarek [1 ]
Elfadel, Ibrahim M. [2 ]
Daniel, Luca [1 ]
机构
[1] MIT, Dept Elect Engn & Comp Sci, Cambridge, MA 02139 USA
[2] IBM Corp, Yorktown Hts, NY 10598 USA
来源
IEEE TRANSACTIONS ON ADVANCED PACKAGING | 2010年 / 33卷 / 04期
关键词
Integrated circuit interconnections; interconnected systems; large scale integration; Markov processes; Monte Carlo methods; parameter extraction; parasitic capacitance; INTEGRAL-EQUATION SOLVER;
D O I
10.1109/TADVP.2010.2091504
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
In this paper, we propose a hierarchical algorithm to compute the 3-D capacitances of a large number of topologically different layout configurations that are all assembled from the same basic layout motifs. Our algorithm uses the boundary element method in order to compute a Markov transition matrix (MTM) for each motif. The individual motifs are connected together by building a large Markov chain. Such Markov chain can be simulated extremely efficiently using Monte Carlo simulations (e.g., random walks). The main practical advantage of the proposed algorithm is its ability to extract the capacitance of a large number of layout configurations in a complexity that is basically independent of the number of configurations. For instance, in a large 3-D layout example, the capacitance calculation of 1000 different configurations assembled from the same motifs is accomplished in the time required to solve independently two configurations, i.e., a 500X speedup.
引用
收藏
页码:818 / 827
页数:10
相关论文
共 26 条
[1]  
Banerjee S., 2008, SPIE C APR, V6925
[2]   Error bounds for capacitance extraction via window techniques [J].
Beattie, MW ;
Pileggi, LT .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1999, 18 (03) :311-321
[3]  
El-Moselhy T., 2009, IEEE ACM INT C COMP
[4]  
El-Moselhy Tarek A., 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), P662, DOI 10.1109/ICCAD.2008.4681647
[5]  
El-Moselhy T, 2008, DES AUT CON, P415
[6]  
Hackbusch W, 1999, COMPUTING, V62, pV
[7]  
Huang PY, 2007, IEEE INT SOC CONF, P283
[8]   Maximization of layout printability/manufacturability by extreme layout regularity [J].
Jhaveri, Tejas ;
Rovner, Vyacheslav ;
Pileggi, Lawrence ;
Strojwas, Andrzej J. ;
Motiani, Dipti ;
Kheterpal, Veerbhan ;
Tong, Kim Yaw ;
Hersan, Thiago ;
Pandini, Davide .
JOURNAL OF MICRO-NANOLITHOGRAPHY MEMS AND MOEMS, 2007, 6 (03)
[9]  
Jiang LJ, 2006, ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING, P331
[10]   Efficient statistical capacitance variability modeling with orthogonal principle factor analysis [J].
Jiang, R ;
Fu, WY ;
Wang, JML ;
Lin, V ;
Chen, CP .
ICCAD-2005: INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN, DIGEST OF TECHNICAL PAPERS, 2005, :683-690