Demonstration of an 8-bit SFQ Carry Look-Ahead Adder Using Clockless Logic Cells

We have designed, fabricated and experimentally demonstrated an 8-bit carry look-ahead adder using clockless AND and NIMPLY cells. A clockless cell is a logic cell without a clock input. Comprared to the circuit using only clocked cells, the circuit using clockless cells has fewer routing wires and splitters. Decrease of the numbers of wires and splitters can reduce the area of a circuit. The 8-bit adder core (without SFQ-to-DC and DC-to-SFQ converters, the clock generator and input and output shift registers for the high frequency test) has 3320 Josephson junctions (JJs) occupying the area of 1.84 mm(2). It is designed for the target operation frequency is 10 GHz with 3 pipeline stages, and the delay from the clock input to the primary outputs of 74 ps at most at the bias voltage of 2.5 mV. The adder chip was fabricated using AIST 10-kA/cm(2) Advanced Process (ADP2) and tested at low and high frequency with measured bias margins of +16%/+6%. The measured maximum frequency was 12.87 GHz.