FPGA-Based Latency-Insensitive OFDM Pipeline for Wireless Research

This paper develops a programmable hardware implementation of the physical layer for cognitive wireless communication systems that use orthogonal frequency division multiplexing (OFDM) schemes. Data-flows within hardware implemented baseband architectures for all communication standards are quite regular in nature, thereby enabling the construction of fast, synchronized and optimized baseband systems on FPGAs. We designed an OFDM pipeline comprising codec, modulation, interleaving, piloting, channel estimation, and IFFT stages in which each stage can be configured at design time or at run time to accommodate different communication standards as well as different configuration settings for a single standard-a key feature necessary for dynamic spectrum sensing and utilization. This flexibility in hardware is achieved by designing each individual stage with room for scaling/modification and having the overall pipeline be insensitive to the latencies incurred by individual pipeline stages. This is done by using stallable stages with centralized control through cross communication between modules both directly and indirectly using code running on the MicroBlaze processor. The OFDM pipeline is implemented on a Xilinx Virtex-6 FPGA and its performance is characterized in terms of functional correctness and FPGA implementation area cost. Experimental results and preliminary simulations of our FPGA based design can run at flexible coding rates of 1/2 and 3/4 with modulation schemes of 4QAM and 16QAM respectively.