A 160MSPS 8-bit pipeline based ADC

被引：0

作者：

Halder, S ^{[1
]}

Ghosh, A ^{[1
]}

Prasad, RS ^{[1
]}

Chatterjeee, A ^{[1
]}

Banerjee, S ^{[1
]}

机构：

[1] IHP Germany, D-15236 Frankfurt, Oder, Germany

来源：

18TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS: POWER AWARE DESIGN OF VLSI SYSTEMS | 2005年

关键词：

double sampling sample-and-hold; comparator; multiplying digital-to-analog converter; pipeline architecture;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents an 8-bit 160-MS/s pipeline analog-to-digital converter using 0.25-micrometer double poly BiCMOS technology of which the total power dissipation is 135mW with 3.3V of analog power supply. The input signal is assumed to be 1V Double sampling technique is used to increase the sampling speed. The sub-circuits are optimized in terms of power and speed. It achieves differential nonlinearity and integral nonlinearity of +/-0.65 LSB and +/-0.8 LSB and an estimated area of 1.60mm(2).

引用

页码：313 / 318

页数：6

共 10 条

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[2]

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[3]

LI YC, 2003, IEEE J SOLID STATE C, V38

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