High-Speed Low-Power True Single-Phase Clock Dual-Modulus Prescalers

A new design technique that improves operating speed of true single-phase clock-based (TSPC) prescalers is presented. We implement dual-modulus prescalers without using any extra logic gates by exploiting the behavior of the second branch in a TSPC flip-flop. The proposed design technique is applied to divided by 2/3 and divided by 3/4 prescalers, and their performances are compared with previous work. Implemented in a 130-nm CMOS technology and compared at same process-voltage-temperature conditions, the maximum speed of the divided by 2/3 prescaler reaches 88% of the maximum operating frequency of a single TSPC flip-flop, and the divided by 3/4 prescaler reaches 75%. In addition, the proposed divide-by- 3 prescaler is able to work almost at the speed of the single TSPC flip-flop. A frequency divider that provides dividing ratios of 7, 8, and 9 is implemented as a part of a 3.4-5-GHz integer-N phase-locked loop in a 130-nm CMOS technology. Simulation and measurement results demonstrate high-speed, low-power, and multiple division ratio capabilities of the proposed technique.