A Versatile and Efficient 0.1-to-11 Gb/s CML Transmitter in 40-nm CMOS

被引：1

作者：

Feng, Jun ^{[1
,2
]}

Beikmirza, Mohammadreza ^{[1
]}

Mehrpoo, Mohammadreza ^{[1
,3
]}

de Vreede, Leo C. N. ^{[1
]}

Alavi, Morteza S. ^{[1
]}

机构：

[1] Delft Univ Technol, ELCA Res Grp, Delft, Netherlands

[2] Katholieke Univ Leuven, MICAS Res Grp, Leuven, Belgium

[3] Broadcom Netherlands, Bunnik, Netherlands

来源：

18TH INTERNATIONAL SOC DESIGN CONFERENCE 2021 (ISOCC 2021) | 2021年

关键词：

D O I：

10.1109/ISOCC53507.2021.9613887

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We present a wireline transmitter (TX) for reconfigurable chip-to-chip links. The proposed design features a frequency-adaptive clock chain, a fast 16:1 clocked-CMOS multiplexer ((CMOS)-M-2 MUX) tree, and a full-rate synchronous current-mode logic (CML) clock driver. A prototype realized in 40-nm CMOS accomplishes a wide 0.1-to-11 Gb/s operation range (f(max)/f(min) = 110x). At 11 Gb/s, the prototype achieves 3.98 pJ/bit for a bit error rate (BER) < 10(-12) with a 60.9-ps eye width.

引用

页码：41 / 42

页数：2

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