Vdd gate biasing RF CMOS amplifier design technique based on the effect of carrier velocity saturation

One of the interesting submicron MOS FET characteristics is the effect of carrier velocity saturation (CVS) on the drain current. In the CVS region, the transconductance becomes constant independent both of the gate and the drain voltage. In this paper, RF MOS amplifier design technique using the CVS region has been proposed. By setting the FET gate bias to the power supply voltage V-dd, stable operation against V-dd Variations can be achieved with a simple circuit configuration. By using this, a 5 GHz amplifier has been designed and fabricated by using 0.18-mu m CMOS process technology. The chip has been operated with a gain variation less than I dB having a peak gain of 13.5 dB from 1.2 to 2.9 V V-dd.