Low-Frequency Noise in Vertically Stacked Si n-Channel Nanosheet FETs

被引:22
作者
de Oliveira, Alberto V. [1 ]
Veloso, Anabela [2 ]
Claeys, Cor [3 ]
Horiguchi, Naoto [2 ]
Simoen, Eddy [2 ]
机构
[1] Univ Tecnol Fed Parana UTFPR, Dept Elect Engn, BR-85902490 Toledo, Brazil
[2] IMEC, B-3001 Heverlee, Belgium
[3] Katholieke Univ Leuven KU Leuven, Dept Elect Engn, B-3001 Heverlee, Belgium
关键词
Carrier number fluctuations; flicker noise; gate-all-around; silicon device; input-referred voltage power spectral density; low-frequency-noise; n-channel; oxide trap density; power spectral density; NANOWIRE TRANSISTORS; 1/F NOISE; ORIENTATION; DENSITY; IMPACT; METAL;
D O I
10.1109/LED.2020.2968093
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This manuscript presents a systematic low-frequency noise analysis of inversion-mode vertically stacked silicon n-channel nanosheet MOSFETs on bulk wafers. Flicker noise due to carrier number fluctuations is shown as the dominant noise source, which is in line with previous reported studies on gate-all-around (GAA) nanowire nMOSFETs. In addition, the benchmark points out that the vertical stacking approach does not deteriorate the oxide trap density, since its normalized input-referred voltage noise Power Spectral Density at flat-band is lower compared to the data on non-stacked horizontal nanowire nMOSFETs. Another finding is that the Coulomb scattering mechanism dominates the mobility.
引用
收藏
页码:317 / 320
页数:4
相关论文
共 34 条
  • [1] Boudier D, 2017, INT CONF ULTI INTEGR, P5, DOI 10.1109/ULIS.2017.7962578
  • [2] Performance Comparison of n-Type Si Nanowires, Nanosheets, and FinFETs by MC Device Simulation
    Bufler, F. M.
    Ritzenthaler, R.
    Mertens, H.
    Eneman, G.
    Mocuta, A.
    Horiguchi, N.
    [J]. IEEE ELECTRON DEVICE LETTERS, 2018, 39 (11) : 1628 - 1631
  • [3] Electronic transport mechanisms in scaled gate-all-around silicon nanowire transistor arrays
    Clement, N.
    Han, X. L.
    Larrieu, G.
    [J]. APPLIED PHYSICS LETTERS, 2013, 103 (26)
  • [4] Colinge JP, 2010, NAT NANOTECHNOL, V5, P225, DOI [10.1038/nnano.2010.15, 10.1038/NNANO.2010.15]
  • [5] Low-Frequency Noise Assessment of Different Ge pFinFET STI Processes
    de Oliveira, Alberto V.
    Simoen, Eddy
    Mitard, Jerome
    Agopian, Paula G. D.
    Martino, Joao Antonio
    Langer, Robert
    Witters, Liesbeth
    Collaert, Nadine
    Thean, Aaron Voon-Yew
    Claeys, Cor
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2016, 63 (10) : 4031 - 4037
  • [6] Threshold voltage extraction methods for MOS transistors
    Dobrescu, L
    Petrov, M
    Dobrescu, D
    Ravariu, C
    [J]. 2000 INTERNATIONAL SEMICONDUCTOR CONFERENCE, VOLS 1 AND 2, CAS 2000 PROCEEDINGS, 2000, : 371 - 374
  • [7] Impact of the Effective Work Function Gate Metal on the Low-Frequency Noise of Gate-All-Around Silicon-on-Insulator NWFETs
    Fang, Wen
    Veloso, Anabela
    Simoen, Eddy
    Cho, Moon-Ju
    Collaert, Nadine
    Thean, Aaron
    Luo, Jun
    Zhao, Chao
    Ye, Tianchun
    Claeys, Cor
    [J]. IEEE ELECTRON DEVICE LETTERS, 2016, 37 (04) : 363 - 365
  • [8] Relation Between the Mobility, 1/f Noise, and Channel Direction in MOSFETs Fabricated on (100) and (110) Silicon-Oriented Wafers
    Gaubert, Philippe
    Teramoto, Akinobu
    Cheng, Weitao
    Ohmi, Tadahiro
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2010, 57 (07) : 1597 - 1607
  • [9] NEW METHOD FOR THE EXTRACTION OF MOSFET PARAMETERS
    GHIBAUDO, G
    [J]. ELECTRONICS LETTERS, 1988, 24 (09) : 543 - 545
  • [10] IMPROVED ANALYSIS OF LOW-FREQUENCY NOISE IN FIELD-EFFECT MOS-TRANSISTORS
    GHIBAUDO, G
    ROUX, O
    NGUYENDUC, C
    BALESTRA, F
    BRINI, J
    [J]. PHYSICA STATUS SOLIDI A-APPLIED RESEARCH, 1991, 124 (02): : 571 - 581