Impact of channel mobility on design optimization of 600-3300 V-class high-speed GaN vertical-trench MOSFETs based on TCAD simulation

To simultaneously evaluate the switching performance and cost (required chip size) of GaN vertical-trench metal-oxide-semiconductor field-effect transistors, we calculated R (on) AR (on) Q (g) considering the Miller effect with various cell pitches, channel mobilities, and blocking voltages. When the blocking voltage was 600 V, optimized cell pitches of 8 and 12 mu m minimized R (on) AR (on) Q (g) with channel mobilities of 100 and 200 cm(2) V-1 s(-1), respectively. Moreover, a wide range of cell pitches could maintain a low R (on) AR (on) Q (g) with a channel mobility of 200 cm(2) V-1 s(-1). This indicates that a channel mobility of 100 cm(2) V-1 s(-1) or higher, particularly 200 cm(2) V-1 s(-1), is desirable for a good switching performance and low cost.