Power-aware scalable pipelined booth multiplier

被引：5
作者：
Lee, H [1 ]
机构：
[1] Inha Univ, Sch Informat & Commun Engn, Inchon 402751, South Korea
来源：
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES | 2005年 / E88A卷 / 11期
关键词：
power-aware; pipelined; Booth multiplier; low-power; design;
D O I：
10.1093/ietfec/e88-a.11.3230
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
An energy-efficient power-aware design is highly desirable for DSP functions that encounter a wide diversity of operating scenarios in battery-powered wireless sensor network systems. Addressing this issue, this letter presents a low-power power-aware scalable pipelined Booth multiplier that makes use of dynamic-range detection unit, sharing common functional units, ensemble of optimized Wallace-trees and a 4-bit array-based adder-tree for DSP applications.
引用
收藏
页码：3230 / 3234
页数：5
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