New in-place strategy for a mixed-radix FFT processor

被引:4
作者
Heo, KL [1 ]
Baek, JH [1 ]
Sunwoo, MH [1 ]
Jo, BG [1 ]
Son, BS [1 ]
机构
[1] Ajou Univ, Sch Elect & Comp Engn, Suwon 442749, South Korea
来源
IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS | 2003年
关键词
D O I
10.1109/SOC.2003.1241467
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
The paper proposes a fast Fourier transform (FFT) processor using a new in-place strategy and the mixed-radix algorithm. The proposed processor uses only two N-word memories for a continuous flow FFT implementation due to the new in-place strategy, while exiting continuous FFT processors use four N-word memories. In addition, the proposed processor satisfies both small area and real-time processing requirement. The gate count of the processor is 37,000 and the number of clock cycles is 640 for a 512-point FFT. Hence, the proposed FFT processor can reduce the gate count and memory size compared with existing FFT processors.
引用
收藏
页码:81 / 84
页数:4
相关论文
共 13 条
[1]  
*AMPH, 2001, CS241081024 POINT FF
[2]  
Choi JR, 2000, ISCAS 2000: IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - PROCEEDINGS, VOL V, P693, DOI 10.1109/ISCAS.2000.857580
[3]  
*DREY ENT INC, 1998, JAG 2 VAR POINT 8 10
[4]   Area-efficient architecture for Fast Fourier Transform [J].
Hidalgo, JA ;
López, J ;
Argüello, F ;
Zapata, EL .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, 1999, 46 (02) :187-193
[5]  
*HOM POW ALL, 2000, HOM 0 5 DRAFT MED IN
[6]  
Jia LH, 1999, 42ND MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, PROCEEDINGS, VOLS 1 AND 2, P804
[7]   CONFLICT FREE MEMORY ADDRESSING FOR DEDICATED FFT HARDWARE [J].
JOHNSON, LG .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, 1992, 39 (05) :312-316
[8]  
LO HF, 2001, P IEEE INT S CIRC SY, P654
[9]  
Radhouane J, 2000, ISCAS 2000: IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - PROCEEDINGS, VOL I, P116, DOI 10.1109/ISCAS.2000.857040
[10]  
*VDSL ALL, 1999, VDSL ALL DRAFT STAND