High-speed, low-power correlated double sampling counter for column-parallel CMOS imagers

被引：27
作者：
Lee, D. [1 ]
Han, G. [1 ]
机构：
[1] Yonsei Univ, Dept Elect & Elect Engn, Seoul 120749, South Korea
来源：
ELECTRONICS LETTERS | 2007年 / 43卷 / 24期
关键词：
D O I：
10.1049/el:20072490
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A high-speed, low-power correlated double sampling counter for column parallel CMOS imagers is proposed. Unlike a conventional up/down counter, the proposed counter performs correlated double sampling using a two's complement arithmetic. The proposed counter can be implemented using only 16 transistors per bit. Simulation results show 32% reduction of power consumption and 2.4 times improvement of maximum speed over a conventional up/down counter.
引用
收藏
页码：1362 / 1364
页数：3
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