Characterising and modelling shared memory accesses in multiprocessor programs

Directory-based, write-invalidate cache coherence protocols are effective in reducing memory latency in shared memory multiprocessors. However, their performance is highly related to the number of coherence actions induced by the application's access pattern. It is therefore important to understand the nature of data sharing access patterns that lead to cache misses for this class of cache coherence protocols. In this paper we identify a set of application parameters that characterises data sharing, the sharing behaviour, for three distinct categories of access patterns: stationary, migratory and producer-consumer accesses. The characterisation can be done in sufficient detail so as to predict the number of cold, coherence and directory replacement misses for a limited-directory cache coherence scheme. To validate a workload model that essentially uses the parameter set as input, a reference generator has been designed. This reference generator is shown to generate the same miss ratio as the workload it models.