DOUBLE SIDE SYSTEM IN PACKAGE DEVELOPMENT CHALLENGE FOR HETEROGENEOUS INTEGRATION

被引:0
作者
Kao, Feng [1 ]
Wang, Yu-Po [1 ]
Wang, Davidlion [1 ]
Tsai, Jensen [1 ]
Tsai, Mike [1 ]
Chiu, Ryan [1 ]
He, Eric [1 ]
机构
[1] Siliconware Precis Ind Co Ltd, Taichung, Taiwan
来源
PROCEEDINGS OF THE ASME INTERNATIONAL TECHNICAL CONFERENCE AND EXHIBITION ON PACKAGING AND INTEGRATION OF ELECTRONIC AND PHOTONIC MICROSYSTEMS, 2019 | 2020年
关键词
Double side SiP; Heterogeneous integration;
D O I
暂无
中图分类号
O414.1 [热力学];
学科分类号
摘要
A Abstracts should be about 200 words. All running text, including the abstract, should be right-justified, in two columns, single-spaced, and in Times New Roman size 10 font. Abstracts - With consumer functionality increasing, more and more active die and passive component integrated into one packaging. Next 5G product design trend is requiring small form factor and better thermal dissipation, original single side product is no larger on optimized solution with larger package size, expensive coreless substrate structure stacked via, in order to accommodate product electrical and characteristic requirement. Considering market driving force toward high performance and lower package cost, double side system in package (SiP) structure is able to realize and fulfill form factor and product characteristic requirement. On this paper, double side SiP package platform will use dual side Surface Mount Technology (SMT) technology and double side molding structure to form outline and also shrink the overall package size. The calculation of package thermal performance can be enhance around 30% and package size can be shrunk around 4b% area, compared to single side SiP which package area could be reduced from 64 mm2 to 36 mm2. With form factor change, product simulation is becoming important in order to mitigate assembly risk. The package characterization are including warpage and thermal simulation. Table1 Basic information comparison for traditional SiP & double side SiP PKG By utilizing advanced package technology and material, such as high speed SMT placement, molding technology, specific copper substrate design and interconnect material integrating into system in package module which provided a unique opportunity to address cost, performance, and time-to-market advantages. The SiP is also a good package platform to consolidate heterogeneous chips. It could be future package trend to accommodate market demand. The SiP structure has proceed the typical reliability testing results as a verification method. Finally, this paper shows the suitable double side SiP structure which can be adopt in smart phone, IoT and wearable devices product application.
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页数:5
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