Instruction-level Instantaneous Power Modeling for VLIW Processor

被引：2

作者：

Zhang, Lichao ^{[1
]}

Wu, Xuetao ^{[1
]}

Zhao, Yiqiang ^{[2
]}

机构：

[1] PLA Informat Engn Univ, Dept Cryptog Engn, Zhengzhou 450001, Henan, Peoples R China

[2] Tianjin Univ, Dept Elect Informat Engn, Tianjin 300072, Peoples R China

来源：

IEEE 12TH INT CONF UBIQUITOUS INTELLIGENCE & COMP/IEEE 12TH INT CONF ADV & TRUSTED COMP/IEEE 15TH INT CONF SCALABLE COMP & COMMUN/IEEE INT CONF CLOUD & BIG DATA COMP/IEEE INT CONF INTERNET PEOPLE AND ASSOCIATED SYMPOSIA/WORKSHOPS | 2015年

关键词：

instruction-level power consumption; modeling; power evaluation; VLIW processor; instantaneous power consumption;

D O I：

10.1109/UIC-ATC-ScalCom-CBDCom-IoP.2015.261

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

Traditional instruction-level power model can evaluate the average power consumption of software, but lacks of the analysis of instantaneous power consumption. In this paper, a cycle-scale accurate power model is established for clustering VLIW structure processor from two aspects, pipeline and instruction code, which can complete instantaneous power evaluation of the processor. Through the implements of different algorithms on a processor, the results show that the model has high accuracy. This model lays a foundation for the research of software's low power compiling.

引用

页码：1451 / 1455

页数：5