Low-power logic synthesis algorithm using multiple partitioning under delay constraints

被引：2

作者：

Choi, IS ^{[1
]}

Hwang, SY ^{[1
]}

机构：

[1] Sogang Univ, Dept Elect Engn, Seoul, South Korea

来源：

ELECTRONICS LETTERS | 1999年 / 35卷 / 07期

关键词：

D O I：

10.1049/el:19990409

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A synthesis algorithm is proposed for the design of a low power combinational circuit under delay constraints. The algorithm partitions a given circuit into several subcircuits, such that only one selected subcircuit is activated at a time, hence reducing unnecessary signal transitions. Experimental results show that the proposed algorithm is efficient for designing low power CMOS digital circuits.

引用

页码：558 / 560

页数：3

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