Automatic optimization techniques for formal verification of asynchronous circuits

被引：0

作者：

Boubekeur, M. ^{[1
]}

Schellekens, M. P. ^{[1
]}

机构：

[1] NUI Cork, Dept Comp Sci, CEOL, Cork, Ireland

来源：

2007 14TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-4 | 2007年

关键词：

D O I：

10.1109/ICECS.2007.4510985

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Even medium size asynchronous circuits may display a complex behavior, due to the combinational explosion in the chronology of events that may happen. It is thus essential to apply automatic optimization techniques to avoid such complexity when formally verifying the correctness of the circuit. This paper presents dedicated techniques for optimization of formal verification of asynchronous circuits, these include for instance: automata reduction, pre-order reduction and automatic abstraction. All these techniques have been implemented and tested in a formal verification environment.

引用

页码：283 / 286

页数：4