A Low-Power Process-Scalable Super-Heterodyne Receiver With Integrated High-Q Filters

被引：57
作者：
Mirzaei, Ahmad [1 ]
Darabi, Hooman [1 ]
Murphy, David [1 ]
机构：
[1] Broadcom Corp, Irvine, CA 92617 USA
来源：
IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2011年 / 46卷 / 12期
关键词：
Bandpass filter; CMOS; image-rejection filter; impedance transformation; N-path filtering; process scalable; receiver; super-heterodyne; zero-IF;
D O I：
10.1109/JSSC.2011.2162909
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A super-heterodyne receiver utilizing integrated high-filters to condition the desired signal to be digitized by a bandpass ADC at an IF of 110 MHz achieves a NF of 2.8 dB and an IIP3 of -8.4 dBm. The conventional M-phase filter is developed to a new form of high-filter that is centered at sum or difference of two clocks. The M-phase filter is also evolved to take two quadrature inputs to perform image rejection, while exhibiting a high-bandpass response with desired signal located in the center. Built of inverters, switches, and MOS capacitors, the receiver follows technology scaling and is reconfigurable through a clock. The receiver including the dividers and LO path draws 12 mA of battery current and occupies 0.76 mm(2) in 65-nm CMOS.
引用
收藏
页码：2920 / 2932
页数：13
相关论文
共 27 条
[1]  
Andrews C., 2010, IEEE ISSCC Dig, P46
[2]   Implications of Passive Mixer Transparency for Impedance Matching and Noise Figure in Passive Mixer-First Receivers [J].
Andrews, Caroline ;
Molnar, Alyosha C. .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2010, 57 (12) :3092-3103
[3]  
[Anonymous], P IEEE CUST INT CIRC
[4]   An 800-MHz-6-GHz software-defined wireless receiver in 90-nm CMOS [J].
Bagheri, Rahim ;
Mirzaei, Ahmad ;
Chehrazi, Saeed ;
Heidari, Mohammad E. ;
Lee, Minjae ;
Mikhemar, Mohyee ;
Tang, Wai ;
Abidi, Asad A. .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2006, 41 (12) :2860-2876
[5]   CMOS mixers and polyphase filters for large image rejection [J].
Behbahani, F ;
Kishigami, Y ;
Leete, J ;
Abidi, AA .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2001, 36 (06) :873-887
[6]   A 13.5-mW 185-Msample/s ΔΣ modulator for UMTS/GSM dual-standard IF reception [J].
Burger, T ;
Huang, QT .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2001, 36 (12) :1868-1878
[7]   3.3-V 240-MS/s CMOS bandpass ΣΔ modulator using a fast-settling double-sampling SC filter [J].
Cheung, VSL ;
Luong, HC .
2004 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2004, :84-87
[8]   d Fully integrated high-Q switched capacitor bandpass filter with center frequency and bandwidth tuning [J].
El Oualkadi, Ahmed ;
El Kaamouchi, Majid ;
Paillot, Jean-Marie ;
Vanhoenacker-Janvier, Danielle. ;
Flandre, Denis .
2007 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS (RFIC) SYMPOSIUM, DIGEST OF PAPERS, 2007, :681-+
[9]   AN ALTERNATIVE APPROACH TO THE REALIZATION OF NETWORK TRANSFER FUNCTIONS - THE N-PATH FILTER [J].
FRANKS, LE ;
SANDBERG, IW .
BELL SYSTEM TECHNICAL JOURNAL, 1960, 39 (05) :1321-1350
[10]   Tunable High-Q N-Path Band-Pass Filters: Modeling and Verification [J].
Ghaffari, Amir ;
Klumperink, Eric A. M. ;
Soer, Michiel C. M. ;
Nauta, Bram .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2011, 46 (05) :998-1010
123