Leveraging Pre-Silicon Verification Resources for the Post-Silicon Validation of the IBM POWER7 Processor

被引：0

作者：

Adir, Allon ^{[1
]}

Nahir, Amir ^{[1
]}

Shurek, Gil ^{[1
]}

Ziv, Avi ^{[1
]}

Meissner, Charles ^{[2
]}

Schumann, John ^{[2
]}

机构：

[1] IBM Res, Haifa, Israel

[2] IBM Server & Technol Grp, Austin, TX USA

来源：

PROCEEDINGS OF THE 48TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC) | 2011年

关键词：

Functional Verification; Post-Silicon Validation; Stimuli Generation; Coverage;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The growing importance of post-silicon validation in ensuring functional correctness of high-end designs has increased the need for synergy between the pre-silicon verification and post-silicon validation. This synergy starts with a common verification plan. It continues with common verification goals and shared tools and techniques. This paper describes our experience in improving this synergy in the pre- and post-silicon verification of IBM's POWER7 processor chip and by leveraging pre-silicon methodologies and techniques in the post-silicon validation of the chip.

引用

页码：569 / 574

页数：6

共 39 条

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