Asynchronous implementation of synchronous esterel specifications

被引:0
作者
Mitra, RS
Bhattacharya, B
Lavagno, L
机构
来源
TENTH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS | 1997年
关键词
embedded systems; executable specifications; hardware software codesign;
D O I
10.1109/ICVD.1997.568106
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
The synchrony hypothesis of Esterel demands the generation of a single monolithic FSM from the specifications. However; for large specifications, the size of this FSM can prove to be inhibitively large. In this paper, we propose a practical solution to this problem, which generates separate FSMs for each of the concurrent instructions. We also enumerate the deviations in semantics due to this translation algorithm so that the user is aware of the executable semantics that he should expect.
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页码:348 / 353
页数:6
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