Cellular Automata (CA) map bits of state on the vertices of a lattice-graph, and compute using a Look-Up Table (LUT), listing the new state of a vertex, given the states of its neighbors. We pursue the long term goal of designing an efficient General-Purpose CA (GPCA). Our current GPCA version uses 77 bits of memory and 13878 logic gates at each vertex. Dealing with such high complexity forced us to develop a new scheme for specifying and simulating CAs. Instead of a lattice-graph we use a planar-graph. We map bits of state not only on vertices, but also on edges and faces of this planar-graph. Computation is not specified with LUT, but using operations on fields of those bits. Fields and operations define a so-called "spatial-type": the 2D space is managed using communication operations moving bits between vertex, edges and faces. Operations are combined into expression computing increasingly complex fields. Expression is the basis of language, it brings two assets: 1-For the specification, expressions for intermediate fields are reused in other higher-level expressions, allowing a modular implementation. 2-For the simulation, an expression is automatically translated in gates and wires of a circuit exploiting the SIMD capabilities of processors. The GPCA represents the supports of agents using a boolean field x. We show how to program incrementally the expression that computes a key intermediate field x (sic). meet(x) representing the set of vertices and edges where modifying x would break the connectedness of a support. We demonstrate the modularity of the description by reusing meet(x) for something it was not planned for in the GPCA: generate a CA circuit computing the Discrete Voronoi Diagram on top of a planar graph.
