共 18 条
- [1] Alsop J, 2019, I S WORKL CHAR PROC, P243, DOI 10.1109/IISWC47752.2019.9041977
- [2] AMD, 2017, Radeons Next-generation Vega Architecture
- [3] Kite: A Family of Heterogeneous Interposer Topologies Enabled via Accurate Interconnect Modeling [J]. PROCEEDINGS OF THE 2020 57TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2020,
- [4] Scalable Distributed Last-Level TLBs Using Low-Latency Interconnects [J]. 2018 51ST ANNUAL IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE (MICRO), 2018, : 271 - 284
- [5] Binkert Nathan, 2011, Computer Architecture News, V39, P1, DOI 10.1145/2024716.2024718
- [6] Choquette Jack, IEEE MICRO
- [8] Lost in Abstraction: Pitfalls of Analyzing GPUs at the Intermediate Language Level [J]. 2018 24TH IEEE INTERNATIONAL SYMPOSIUM ON HIGH PERFORMANCE COMPUTER ARCHITECTURE (HPCA), 2018, : 608 - 619
- [9] Hesse Robert, 2015, PROC 9 INT S NETW CH, P1
- [10] Jerger Natalie D. Enright, 2017, ONCHIP NETWORKS