A clock-tuning circuit for system-on-chip

被引:18
作者
Elboim, Y
Kolodny, A
Ginosar, R
机构
[1] Oren Semicond Ltd, Yoqneam, Israel
[2] Technion Israel Inst Technol, Dept Elect Engn, VLSI Syst Res Ctr, IL-32000 Haifa, Israel
关键词
circuit tuning; clock distribution; inserted delay; intellectual property (IP) core; system-on-chip (SoC);
D O I
10.1109/TVLSI.2003.812371
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
System-on-chip (SoC) design depends heavily on effective reuse of semiconductor intellectual property (IP). Clock distribution has become a problem for integrating IP cores into a single synchronous SoC, because of different clock delays in the IP cores. We propose an onchip clock-tuning circuit, which enhances design flexibility. Programmable delays are inserted in the clock distribution network, such that clock alignment and synchronization are achieved. Design iterations are eliminated with the use of the tuning circuit, saving design effort, and cost. The method is also applicable to compensating for unbalanced clock trees. Hierarchical clock tuning can be implemented and can take advantage of the hierarchical structure of the SoC. Skew analysis has shown that the added programming unit outperforms other clock design options. The method was implemented in a commercial chip, and demonstrated good functionality with high productivity of the design flow.
引用
收藏
页码:616 / 626
页数:11
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