In this work of low power memory design on FPGA, we are using the most energy efficient I/O standard among LVCMOS, HSLVDCI, HSTL, LVDCI_DV2 and SSTL. I/O standard is used to match impedance of transmission line, impedance of port and impedance of memory for avoidance of transmission line reflection. In naming convention of I/O Standard, LV is Low Voltage, HS is High Speed, DV2 is Half Impedance, CMOS is Complementary Metal Oxide Semiconductor, DCI is Digitally Control Impedance and SSTL is Stub Series Transistor Logic. We are saving 94.28%, 94.26%, 32% power with LVCMOS in place of SSTL, HSTL, and HSLVDCI respectively. We are also saving 95.29%, 95.27%, 44%, 17.65% power using LVDCI_DV2 in comparison to SSTL, HSTL, HSLVDCI and LVCMOS respectively. Xilinx Planahead 13.4 and Xilinx Power 13.4 is used as simulator in order to synthesize, simulate, and implement low power RAM-UART memory interface design on this FPGA. XPower analyzer is used for power analysis.
