Yield Improvement and Test Cost Optimization for 3D Stacked ICs

被引:7
作者
Hamdioui, Said [1 ]
Taouil, Mottaqiallah [1 ]
机构
[1] Delft Univ Technol, Comp Engn Lab, Fac EE Math & CS, NL-2628 CD Delft, Netherlands
来源
2011 20TH ASIAN TEST SYMPOSIUM (ATS) | 2011年
关键词
3D Stacked IC; Yield; Layer Redundancy; Test Flows;
D O I
10.1109/ATS.2011.88
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Three-Dimensional Stacked IC (3D-SIC) is an emerging technology promising many benefits, such as heterogeneous integration, reduced latency and power consumption. Realizing higher compound yield and overall low cost are the driving forces of the success of such a technology. This paper addresses these two topics. First, two yield improvement schemes will be discussed: wafer matching and layer redundancy. Wafer matching is a technique that can be applied when Wafer-to-Wafer (W2W) stacking is used to fabricate 3D-SICs; this stacking approach provides many advantages such as high throughput, thin wafer and small die handling, and high TSV density; however, it suffers from low compound yield as compared with other stacking processes. Layer redundancy, on the other hand, is based on adding redundant layer(s) to the stacked IC to replace the faulty irreparable dies in the stack. It can be applied only when similar dies are stacked as it is the case for stacked memories. Experiment results for both wafer matching and layer redundancy will be presented and compared; they show that both wafer matching and layer redundancy significantly improve the yield and therefore reduce the cost per 3D-SIC. Second, test cost optimization will be covered. During the manufacturing of 3D-SICs, tests can be applied at different moments such as before the stacking process, during the creation of each partial stacked IC, after the creation of the complete stack, etc. This results into a huge number of test flows. A framework covering different test flows will be discussed. In addition, an appropriate cost model able to identify the most cost-effective test flow will be presented. The simulation results show that test flows with the pre-bond testing significantly reduce the overall cost, that a cheaper test flow does not necessary results in lower overall cost, and that the best cost-effective test flow strongly depends on the stack yield; hence, adapting the test according the stack yield is the best approach to use.
引用
收藏
页码:480 / 485
页数:6
相关论文
共 19 条
[1]  
Adams R., 2003, HIGH PERFORMANCE MEM
[2]  
[Anonymous], IEEE ACM INT C COMP
[3]  
[Anonymous], IEEE T VERY LARGE SC
[4]   Cost-Effective Integration of Three-Dimensional (3D) ICs Emphasizing Testing Cost Analysis [J].
Chen, Yibo ;
Niu, Dimin ;
Xie, Yuan ;
Chakrabarty, Krishnendu .
2010 IEEE AND ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD), 2010, :471-476
[5]  
Chou CW, 2010, 2010 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN AUTOMATION AND TEST (VLSI-DAT), P104, DOI 10.1109/VDAT.2010.5496702
[6]   Demystifying 3D ICs: The procs and cons of going vertical [J].
Davis, WR ;
Wilson, J ;
Mick, S ;
Xu, M ;
Hua, H ;
Mineo, C ;
Sule, AM ;
Steer, M ;
Franzon, PD .
IEEE DESIGN & TEST OF COMPUTERS, 2005, 22 (06) :498-510
[7]  
Garrou P., 2008, HDB 3D INTEGRATION
[8]   Processor design in 3D die-stacking technologies [J].
Loh, Gabriel H. ;
Xie, Yuan ;
Black, Bryan .
IEEE MICRO, 2007, 27 (03) :31-48
[9]  
Marinissen Erik Jan, 2009, Proceedings of the 2009 IEEE International Test Conference (ITC 2009), DOI 10.1109/TEST.2009.5355674
[10]   Yield and cost modeling for 3D chip stack technologies [J].
Mercier, P. ;
Singh, S. R. ;
Iniewski, K. ;
Moore, B. ;
O'Shea, P. .
PROCEEDINGS OF THE IEEE 2006 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2006, :357-360