Optimal design of clock trees for multigigahertz applications

被引:9
作者
Escovar, R [1 ]
Suaya, R [1 ]
机构
[1] Mentor Graph Corp, F-38334 Saint Ismier, France
关键词
circuit optimization; clocks; delay estimation; inductance;
D O I
10.1109/TCAD.2004.823350
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
With the onset of gigahertz frequencies on clocked digital systems, inductance effects become significant. We investigate appropriate regimes where signal, propagation on an IC can be characterized as resulting from transmission line (TL) behavior. The signals propagate at a speed in the proximity of the speed of light in the medium. Our starting points are exact solutions in the time domain to the TL equations. A methodology to evaluate the feasible domains of physical and electrical variables that permit TL propagation is given. We develop fast and accurate computational methods for inductance and capacitance calculations. A general expression of the time delay in the presence of finite rise time and finite load capacitance for TL propagation is derived. We analyze a clock-synthesis method based on sandwiched balanced H-trees consistent with TL propagation. We find the feasible physical domains by solving iteratively two nonlinear equations in a space spanned by two continuous variables, with four parameters. To further assert its applicability we remove common assumptions such as the constancy of the electromagnetic parameters, zero rise time, and load capacitance. The spectrum of configurations is satisfactory at 130 nm and scales well into the 45-nm generation.
引用
收藏
页码:329 / 345
页数:17
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