Impact of Process Variations on Negative Capacitance FinFET Devices and Circuits

被引:45
作者
Dutta, Tapas [1 ]
Pahwa, Girish [1 ]
Agarwal, Amit [2 ]
Chauhan, Yogesh Singh [1 ]
机构
[1] IIT Kanpur, NanoLab, Dept Elect Engn, Kanpur 208016, Uttar Pradesh, India
[2] Indian Inst Technol, Dept Phys, Kanpur 208016, Uttar Pradesh, India
关键词
Negative capacitance; FinFET; ferroelectric; process variation; 7 nm technology node; Monte-Carlo simulations; VOLTAGE AMPLIFICATION;
D O I
10.1109/LED.2017.2770158
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
We report on the impact of process variations on short-channel negative capacitance (NC)-based FinFETs through statistical Monte Carlo simulations using a physics-based model of NC-FinFETs. We find that relative to regular FinFETs, the impact of geometrical variability can be lesser or higher in NC-FinFETs in different regimes of device operation and is strongly dependent on the nominal ferroelectric (FE) thickness (t(fe)). The contribution of the FE layer to the overall variability behaves non-monotonically with increase in the nominal tfe. While the OFF-current and threshold voltage variabilities scale down, the ON-current variability does not follow a monotonic trend with increase in the nominal t(fe). We also show that although relative to the regular FinFET-based ring oscillator (RO) circuit, the NC-FinFET-based RO (NC-RO) circuit displays increased immunity to process variation induced delay variability, the trend is non-monotonic with regard to tfe scaling.
引用
收藏
页码:147 / 150
页数:4
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