Analysis of Ultralow-Power Asynchronous ADCs

被引：0

作者：

Balasubramanian, Viswanathan ^{[1
]}

Heragu, Aravind ^{[1
]}

Enz, Christian ^{[1
]}

机构：

[1] Ecole Polytech Fed Lausanne, Lausanne, Switzerland

来源：

2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS | 2010年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, analysis of a novel class of A/D converters based on asynchronous delta modulation (DM) is presented and a high level model is realized for the same. Using the high level model, analytical expressions are derived for the calculation of the inband signal-to-quantization noise ratio (SQNR) for the case of sinusoidal inputs and two-tone inputs. For the special case of sinusoidal inputs, an empirical formula is also derived for calculating the inband SQNR. The derived analytical and empirical expressions are verified using high level simulations and the simulation results are presented finally.

引用

页码：3593 / 3596

页数：4

共 5 条

[1] A 120nm low power asynchronous ADC
Allier, E
Goulier, J
Sicard, G
Dezzani, A
André, E
Renaudin, M
[J]. ISLPED '05: PROCEEDINGS OF THE 2005 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, 2005, : 60 - 65
[2] QUANTIZATION NOISE SPECTRA
GRAY, RM
[J]. IEEE TRANSACTIONS ON INFORMATION THEORY, 1990, 36 (06) : 1220 - 1244
[3] A level-crossing sampling scheme for A/D conversion
Sayiner, N
Sorensen, HV
Viswanathan, TR
[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 1996, 43 (04) : 335 - 339
[4] Analysis of continuous-time digital signal processors
Schell, Bob
Tsividis, Yannis
[J]. 2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, 2007, : 2232 - 2235
[5] A Continuous-Time ADC/DSP/DAC System With No Clock and With Activity-Dependent Power Dissipation
Schell, Bob
Tsividis, Yannis
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2008, 43 (11) : 2472 - 2481

← 1 →