Design of Ultra Lowpower Full Adder using Modified Branch Based Logic Style

In this paper a novel method has been proposed for the problem of repeating a transistor controlled by the same input in two parallel branches in Branch Based Logic-Pass Transistor Full Adder (BBL-PT FA). In BBL-PT FA carry block is designed by using branch based logic style and sum block is with pass transistor logic style. The modifications are done for carry block. Common transistor in parallel branches is taken out and kept one transistor for parallel branches. This method provides advantages of reduced number of transistors, decrease in die area of the design, and power dissipation. Designed circuits are simulated using spectre simulator in virtuoso tool provided by Cadence Design Systems Electronic Design Automation (EDA) tool. Simulations have been done using Generic Process Design Kits 180, 90, and 45 nanometer technology files with supply voltage of 1.8V, 1.2V, 1.1V respectively and operating frequency 500MHz. Simulation results show that the proposed solution gives better results.